Intregrated Circuit ( IC ) Delayering
Within the semiconductor industry, the business to tear down, deconstruct, or deprocess wafer level integrated circuits (IC) exists. This deconstruction process is pursued to conduct failure analysis and reverse engineering of the internal structure of the IC device. The IC’s are small chips which may have an areal size of 4mm x 4mm or larger with dimensions like 25mm x 25mm. The IC’s have a Silicon substrate base on top of which are grown very thin layers of electronic materials which form components in microelectronic circuits. These layers are micrometer to nanometer thick and consist of a complex array of conductive metals, insulating dielectrics and semiconductor materials. The typical number of layers can range from 5 to 12. A simple single layer may consist of Aluminum lines, Copper posts embedded in a SiO2 matrix with interspersed active doped-Silicon structures.
Industrial demand to analyze the failure mode or reverse engineer these complicated IC structures requires the layers to be precisely and uniformly exposed layer by layer. By necessity of the IC construction, the layers which are first exposed are the outer ones. Then to reach deeper layers, the layers are sequentially removed layer by layer. This removal technique is called delayering. The historic and standard delayering techniques are bumping-up against their limitations to handle the contemporary IC chip designs.
As the microelectronics market moves to push more powerful and densely populated IC chips, contemporary IC designs are increasingly shrinking the layer thicknesses and compacting the structures within the layers. Using the established techniques to delayer the contemporary IC chips, has become tediously costly, error prone and with limited utility. In order perform failure analysis and reverse engineering on contemporary IC chips, the delayering process requires new material removal methods which can precisely remove nanometer amounts of these electronic materials over the entire area of the IC chip.
In general, the primary objective in the delayering process would be to remove material in a manner which exposes the constitutes in a common plane of the IC chip. A failed delayering step would penetrate adjacent layers, revealing material and structures not relevant to the plane which is to be studied. The delayering process techniques need to be adept at creating a common planar surface which is smooth and uniform. The challenge confronting delayering techniques is the scale at which it performs. It must control the accurate removal of micrometer, nanometer and atomic levels of surface material. The challenge is compounded because it is not a single well identified material which is removed, but rather the surface will consist of different materials. The unique properties of these materials make them behave differently when exposed to delayering processes. The removal characteristics of the materials differ by their natural properties. Therefore, delayering employs various tactics to control removal rates while producing a flat, planar surface at the micrometer scale.
Common Delayering Method
Fundamentally, delayering can be defined to be an etching process. Etching is the removal of material from a solid surface which is in contact with the etchant. The common and established delayering methods include:
Wet Chemical Etch is where liquid reactants are in contact with the IC chip creating a reaction with the surface materials. The reaction products are gases or liquid which diffuse away from the IC layer. The wet etch method can suffer from chemical selectivity shortcomings where reactants do not react with all the IC surface materials in a manner which provides the desired layer, leaving a mixed surface which would require additional steps to remove remnants.
Mechanical Polishing is where the polishing tools are employed to remove surface material. This technique uses the application of force and slurries to physically remove material. This method is susceptible to uneven application of force and makes it difficult to control planarization. The technique is vulnerable to residual contamination and damage from the polishing compounds or slurries, plus layer non-uniformities are a risk which exposes multiple layers and not the desired common layer.
Dry Plasma Etch is where the IC chip is immersed in a gaseous plasma which is a mixture of atoms, neutral radicals, ions and electrons. Through means of electrostatic forces and gas kinetics, the ions and radicals arrive on the IC surface, removing material by either a physical sputter or dry chemical etching mechanism. This dry plasma etch method is a simple and basic material removal technology which suffers because of its inherent physical limitations and rudimentary control capabilities. For example, this method struggles to etch Copper at a meaningful rate even with the incorporation of special tactics such as using very corrosive gases.
ION BEAM ETCHING ( IBE) TECHNOLOGY
With these prevailing methods falling short of the trending requirements to delayer contemporary IC chips, but broad ion beam etching (IBE) technology to satisfy the new performance demands confronting delayering processes. Utilizing inherent properties of ion beam etching (IBE) technique, scientists are researching and developing fabrication processes which match new delayering goals driven by the failure analysis and reverse engineering on contemporary IC chips. The IBE PROCESS METHOD ADVANCES DELAYERING OUTCOMES, including tight layer planarization, nanometer etch layer precision, universal material removal and removal uniformity across layer when compared to the prevailing methods.
Ion Beam Etching is a dry plasma etch method which utilizes a remote broad ion beam source to remove IC chip material by physical inert gas means and chemical reactive gas means. From this remote ion source, a directed and neutralized ion beam is accelerated towards the IC chip. Ion beam etching independently and precisely controls critical material removal properties such as etch rate, etch material selectivity, surface planarization, and material removal uniformity over the entire IC chip surface. This level of control over the entire IC chip surface is unique to ion beam etching approach.
Given below is a list of these unique properties which have been explored to address the new IC chip delayering objectives and overcome the shortcomings of the prevailing methods.
UNIQUE PROPERTIES OF IBE
1) Ion beam etching (IBE) has the capability to remove any material by a purely physical process. This process is sometimes called sputtering. Considered a universal etchant process method, IBE can etch metals, alloys, insulators, semiconductors, carbon-based materials and any multilayers or composites thereof. IBE can accurately control the rates of removal of these materials by its ability to precisely control the ion beam properties. These ion beam properties such ion energy, ion current density, incidence angle fundamentally determine the physical sputtering phenomena.
2) By selecting the correct feed gases when designing the ion beam etch process, the etch rates of materials can be optimized to preferentially remove one material over another. This optimization is called material etch selectivity. In ion beam etching, the ability to include variable process gases promotes and supports similar removal rates of the different materials found in an IC layer. The uniform removal of different materials produces quality common planar surfaces sought in delayering.
3) Ion beam etching will remove tens of micrometers of material which is well suited to etch the IC’s thick upper passivation layer. But, it’s the capability to precisely and repeatability remove atomic levels of material which is a key advantage in the delayering field. The IBE process range of operation enables gentle removal rates which allows delayering resolution at the nanometer scale. The predictability of this precision control to stop on the desired layer overcomes the undershoot or overshoot risks in the prevailing methods.
4) The surface of the IC chip does not always present a flat starting layer. Some of the top layers may have structures which protruded from the layer. A good delayering method will possess the ability to planarize or smooth the surface, removing these protruded features. Ion beam etching is uniquely suited to etch these structures with its capability control the incidence angle of the beam as it strikes the surface. In doing so, it can enhance the removal selectivity of these elevated structures over the base layer, eventually smoothing out the layer. Without the use of polishing slurries as done with mechanical force polishing, ion beam etching polishes the surfaces by removing material on the atomic/molecular scale.
5) The size of the broad ion beam is large when compared to IC chips. Therefore, ion beam etching is naturally suited to uniformly remove material from IC layers. The even distribution of processing power across a 25mm x 25mm IC chip can etch material with less than 1% non-uniformity. Consequently, the objective to form a common layer and propagate common layers deeper into the IC structure is readily achievable with our ion beam etching method.
6) When compared to the prevailing methods, ion beam etching does not present the invasive side-effects that can distort the layer and interfere with the integrity of the subsequent measurements and analysis. Ion beam etch avoids the residual contamination and damage as might occur with mechanical polishing methods. Ion beam etching avoids layer corrosion or percolation of fluid chemicals to lower layers in the IC as might happen in the wet chemical etch. In ion beam etching, the IC chip is not immersed in a high-density plasma as in the dry plasma etch method. When the IC chip is immersed in the plasma it is exposed to heat and radiation which can possibly alter surface material from its native state. Ion beam etching minimizes exposure to the bulk plasma, therefore reducing temperature and radiation concerns.